Engineering properties of ring shaped polytheylene terephthalate (RPET) fiber self-compacting concrete

Polyethylene terephthalate (PET) bottles are plastic containers that are typically discarded, and thus, cause environmental pollution. To solve this problem, PET bottles are recycled in concrete. Previous studies have mostly used PET with straight or irregularly shaped fibers. It has been shown that PET has a weak interfacial bond with cement paste in the pullout load because of the lamellar shape of fibers. Therefore, ringshaped PET (RPET) fibers are introduced in this study to overcome the limitations of traditional straight, lamellar, or irregularly shaped fibers. RPET fibers are mainly designed with a special shape to mobilize fiber yielding rather than fiber pullout. RPET fibers are made directly from waste bottles. The diameter of RPET bottles is fixed at 60 ± 5 mm. The width of RPET fibers is fixed at 5, 7.5, or 10 mm and designated as RPET-5, RPET-7.5, and RPET-10 respectively. This study mainly determines the optimum water– binder ratio and fiber content of RPET fiber concrete (FC) through self-compacting, as well as through compressive, tensile, and toughness strength tests. A water–binder ratio of 0.55 and working ranges from 0.25% to 1% of fiber content are successfully accepted for all sizes of RPET fibers. Result of the pullout test shows that RPET fiber interfacial bond strength ranges from 0.502 MPa to 0.519 MPa for RPET-5 fiber, from 0.507 MPa to 0.529 MPa for RPET-7.5 fiber, and from 0.516 MPa to 0.540 MPa for RPET-10 fiber. This study presented that the compressive and tensile strength of RPET fiber exhibited an increase of 17.3% and 35.7%, respectively compared to normal concrete. RPET FC shows improvement in first crack load for flexural toughness strength of RPET FC with increase of 24.5% compared to normal concrete specimen. Moreover, 156 FC cylinders were used to develop new equations for predicting the compressive and tensile strengths of RPET FC via multiple regression analysis. Two equations are obtained. These equations are included in calculating compressive and tensile strength of RPET FC limited up to 28 days In conclusion, incorporating RPET fibers when recycling waste PET bottles in concrete produces FC with An improvement performance comparable to that of normal concrete

Fault Detection with Optimum March Test Algorithm

This paper presents a research work aimed to detect previously-undetected faults, either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both in March Algorithm such as MATS++(6N), March C-(10N), March SR(14N), and March CL(12N). The main focus of this research is to improve fault coverage on Single Cell Faults as well as Static Double Cell Faults detection, using specified test algorithm. Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds) and Deceptive Read Destructive Faults (CFdrds) are types of faults mainly used in this research. The experiment result published in [1] shows BIST (Built-In-Self-Test) implementation with the new algorithm. It provides the same test length but with bigger area overhead, we therefore proposed a new 14N March Test Algorithm with fault coverage of more than 95% using solid 0s and 1s Data Background (DB). This paper reveals the design methodology to generate DB covers all memories function by applying non-transition data, transition data, and single read and double read data. The automation hardware was designed to give the flexibility to the user to generate other new March Algorithm prior to the selected algorithm and analyzed the performance in terms of fault detection and power consumption

Fault detection with optimum March test algorithm

This paper presents a research work aimed to detect previously-undetected faults, either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both in March Algorithm such as MATS++(6N), March C-(10N), March SR(14N), and March CL(12N). The main focus of this research is to improve fault coverage on Single Cell Faults as well as Static Double Cell Faults detection, using specified test algorithm. Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds) and Deceptive Read Destructive Faults (CFdrds) are types of faults mainly used in this research. The experiment result published in [1] shows BIST (Built-In-Self-Test) implementation with the new algorithm. It provides the same test length but with bigger area overhead, we therefore proposed a new 14N March Test Algorithm with fault coverage of more than 95% using solid 0s and 1s Data Background (DB). This paper reveals the design methodology to generate DB covers all memories function by applying non-transition data, transition data, and single read and double read data. The automation hardware was designed to give the flexibility to the user to generate other new March Algorithm prior to the selected algorithm and analyzed the performance in terms of fault detection and power consumption

Testing static single cell faults using static and dynamic data background

This work proposes a bit-adjacent Data Background (DB) management scheme to improve fault coverage of March algorithms while simultaneously maintaining the shortest test cycle. Both static and dynamic DB transitions are used in order to detect Deceptive Read Destructive Faults (DRDFs) and Write Disturb Faults (WDFs) that are not detected by previous algorithms. A conventional March Test Algorithm can be modified by using the DB management scheme to form a new March Test Algorithm (referred to as Mod March Test Algorithm), e.g., MATS++(6N) becoming Mod MATS++(6N). This paper shows that Mod March SR (14N) and Mod March CL (12N) can detect DRDFs and WDFs while the corresponding conventional algorithms cannot. It is also shown that Mod March CL(12N) and Mod March SR(14N) with DB management can detect all Static Single Cell Faults based on the Bit-Oriented-Memories (BOM) test method. Comparisons on test cycle time for Mod March SR, March SR, and March SS in the context of memory Built-In-Self-Test (BIST) are also presented. From the simulation result, it shows that by including Data Backgrounds (DBs) management in Bit-Oriented Memories (BOM), the cycle test time is the same after a given multiple of DBs in the test algorithm

Rounded off unsigned constant division using add-shift in verilog

Even when sophisticated synthesis strategies are already being used to optimise the delay, area and power dissipation of Asic implementation, the quality of the results still heavily depend on the quality of the Register Transfer Level (RTL). In RTL design, multiplication and division by a constant number that is a power of two (e.g. 2, 4) can be done using the left shift (multiplication) and the right shift (division). Yet systems commonly multiply and divide by another constant number, such as by 3 or 7. It is also discovered that the implementation of division in hardware is expensive in term of area. This however can be overcomed by replacing the division with a cheaper adder and shifter (add-shift) that produces the same result. This paper presents the logic synthesis result of the add-shift scheme that was modified from existing algorithm and was described in Verilog code. The constant denominators (deno) were 3, 5, 6, 7 and 9 and the input variables (n) were of 13 bits. The modifications were to eliminate the integer multiplication, round off the unsigned result and maximise the sharing of common partial quotients for the five divisors. The logic synthesis was performed using Synopsis Design Compiler on two different technology libraries. Both 0.18µm Siltera and MIMOS 0.35µm technology libraries showed a significant optimization on power dissipation compared to normal division. However, the area was not optimized neither on Siltera nor MIMOS technology library

Anti-inflammatory and anti-pyretic properties of spirulina platensis and spirulina lonar: a comparative study

Spirulina spp. is a blue-green algae belongs to the family of Oscillatoriaceae, which having diverse biological activity. The aim of this current study was to evaluate and compare the anti-pyretic and anti-inflammatory activity of Spirulina platensis/SP and Spirulina lonar/SL extracts. In the anti-pyretic study, the ability to reduce the rectal temperature of rats induced pyrexia with 2g/kg Brewer’s Yeast (BY) was performed. Rats were dosed either 2 or 4 mg/kg SP or SL. Rectal temperature was taken every hour for 8 hours. Results shown that there were significant dosedependent (p<0.05) reduction of both treatments. However, SP treatment revealed faster reduction in rectal temperature. For anti inflammatory activity, the reduction in the volume of paw edema induced by Prostaglandin E2 (100 IU/rat intraplantar) was measured. Rats were dosed orally with 2 or 4 mg/kg SP or SL. The paw edema was measured every 30 minutes for 4 hours using plethysmometer. Results had shown a significant dose dependent reduction in diameter of paw edema (p<0.05). The finding suggests that SP and SL extracts have anti-pyretic and anti inflammatory properties. However, SP was found to be more effective than SL as anti-pyretic and anti-inflammatory agent

Multiple and solid data background scheme for testing static single cell faults on SRAM memories

Memory testing is a method that requires an algorithm capable of detecting faulty memory as comprehensively as possible to facilitate the efficient manufacture of fault free memory products. Therefore, the purpose of this thesis is to introduce a Data Background (DB) scheme to generate an optimal March Test Algorithm (MTA) for detecting faults of memory that are undetectable using existing algorithms. The present research focuses on two types of Static Single Cell Faults (SSCFs): Write Disturb Faults (WDFs) and Deceptive Read Destructive Faults (DRDFs). These faults are undetectable by existing algorithms with insufficient operation. To date, the main effort in this field of research is to improve fault detection by modifying or adding an operation sequence in the MTA. A relatively small number of test approaches have worked on the DB scheme instead of the MTA to improve fault coverage. However, these approaches were designed to improve the fault coverage for detectable faults only. Thus, the present research develops a new DB scheme to be applied to existing MTA to detect two WDFs and two DRDFs. Two methods are proposed in this project. In Method 1, a multiple DBs generator with a bit-adjacent DB management scheme is applied for the selected MTA. This method is evaluated in terms of function and performance differences between the proposed MTA and existing MTA using the User Defined Algorithm (UDA) available in the MBISTArchitect tool. Findings show that both MTAs have the same testing time. However, the existing MTA of the Memory Built-In-Self Test (MBIST) required a bigger area overhead and consumed more power. Hence, Method 1 is not suitable to be used with the MBIST for System on Chip (SoC). For Method 2, suitable solid DBs are used to provide higher fault coverage instead of using the existing MTA. The new MTA is defined by designing an automation program called DB generator. The DB generator computes all the possible DBs and filters the list of preferable DBs using efficient combination logic. The proposed MTA is obtained after the eliminating procedure of the preferable DB list using the SQ generation rule. Finally, the fault coverage will be calculated manually by doing fault evaluation analysis using Fault Primitives (FP) rules. Results show that WDFs and DRDFs are successfully detected with each proposed MTA. The proposed MTAs are also able to detect other SSCFs, such as Transition Fault, Stuck-At Fault, Incorrect Read Fault, Read Destructive Fault, and State Fault. Finally, based on the SQ generation rule, and the development of the DB generator, MTAs are generated. The present research demonstrates that the DB generator and proposed MTAs, such as March CL-1, March Cl-2, March SR-1, and March SR-2, are successfully applied and designed, with up to 100% fault coverage